1. Field of the Invention.
The present invention relates to hybrid circuits which comprise both superconducting and semiconducting devices, and also relates to hybrid circuits which comprise semiconducting devices, superconducting devices and hybrid superconducting-semiconducting devices. More particularly, this invention relates to the application of these combinations of devices in novel circuits to perform the function of random access memory.
2. Description of the Related Art.
There are three main areas of related prior art. The first is the prior art on superconducting-semiconducting circuits which is described in the U.S. patent application Ser. No. 07/518,004 titled "Superconducting-Semiconducting Circuits, Devices and Systems" by the present inventors and which has been allowed by the United States Patent and Trademark Office, and in a second U.S. patent application Ser. No. 07/638,911 by the present inventors, titled "Hybrid Superconductor-Semiconductor Crossbar Circuit". Issues concerning interconnection circuits are also described in U.S. Pat. No. 4,980,580, titled "CMOS Interconnection Circuit" by Ghoshal and a related publication, U. Ghoshal, "CMOS Inter-Chip Interconnection Circuit Using High-Tech Superconducting Tunnel Junctions and Interconnections," IEEE Electron Device Letters, vol. 10, pp. 373-76, August 1989.
The second area of prior art includes all the extensive literature on semiconductor memory circuits. The state-of-the-art circuit techniques in semiconductor dynamic random access memories are summarized in a recent publication, K. Itoh, "Trends in Megabit DRAM Circuit Design," IEEE I. Solid-State Circuits, vol. 25, pp. 778-89, June 1990, whereas recent literature about other types of semiconductor memories can be found in the October 1990 issue of the IEEE Journal of Solid-State Circuits. Some issues regarding low temperature operation of CMOS memory circuits at 77 kelvins are described in the publications: T. Chappell, S. Schuster, B. Chappell, J. Allan, J. Sun, S. Klepner, R. Franch, P. Greier and P. Restle, "A 3.5 ns/77 K. and 6.2 ns/300 K. 64K CMOS RAM with ECL Interfaces," IEEE J. Solid-State Circuits, vol. 24, pp. 859-67, August 1989; and R. Jaeger and T. Blalock, "Quasi-Static RAM Design for High Performance Operation at Liquid Nitrogen Temperature," Cryogenics, vol. 30, pp. 1030-35, December 1990.
The third area of related prior art is the technical literature on superconducting Josephson memory circuits. The early designs by the IBM group have been summarized in H. Zappe, "Memory-Cell Design in Josephson Technology," IEEE Trans Electron Devices, vol. ED-27, pp. 1870-82, 1980 and in S. Faris, "Basic Design of a Josephson Technology Cache Memory," IBM J. Res. Develop. vol. 24, pp. 143-66, 1980. Recent demonstrations and designs are summarized in the review article Wada, "Josephson Memory Technology," Proc. IEEE, vol. 77, pp. 1194-1207, 1989.
The first area of the related art describes the utility of combining superconducting devices and semiconducting devices preferably, but not necessarily, in the same integrated circuit chip. Specifically, the above-mentioned U.S. patent application Ser. No. 07/518,004 describe how it is possible to construct an amplifier from conventional CMOS transistors and Josephson devices that can provide amplification of Josephson-level voltages (typically of the order of 3 mV for low-temperature superconductors and of the order of tens of millivolts for high-temperature superconductors) to the voltage levels useful as inputs to conventional CMOS circuits (of the order of hundreds of millivolts). The amplifiers described in the patent application and publication occupy a small area and have short delays.
Another part of the related prior art on hybrid superconductor-semiconductor circuits describes the utility of the presently available superconducting field effect transistors (SFETs) to be useful in practical circuits if the semiconductor-to-superconductor interface circuits are realized. See A. Kleinsasser and W. Gallagher, "Three-terminal devices," in Superconducting Devices, Eds. S. Ruggiero and D. Rudman, San Diego: Academic Press, 1990, Chapter 9, and T. Nishino, M. Hatano, H. Hasegawa, F. Murai, T. Kure, A. Kiraiwa, K. Yagi and U. Kawabe, "0.1 .mu.m gate-length superconducting FET," IEEE Electron Device Letters, vol. 10, pp. 61-63, February 1989. As described in U.S. patent applications Ser. Nos. 7/518,004 and 7/518,005, SFETs are devices which can both conduct a zero-voltage Josephson current, and also can be turned off (conduct only an insignificantly small current with a non-zero drain-to-source voltage drop) by application of a proper control voltage. Presently known SFETs cannot by themselves develop a sufficiently high voltage to provide the voltage necessary to control other SFETs, and thus lack the voltage gain to be useful as restoring ratioed logic gates. In complementary structures, SFETs might achieve voltage gain, but cannot achieve substantial performance improvements beyond the conventional CMOS devices. However, if the SFETs are used along with the CMOS amplifier circuits disclosed in U.S. patent application Ser. Nos. 7/518,004 and 7/518,005, novel pass-transistor circuits can be realized. The availability of the superconducting-to-semiconducting interface amplifiers is, therefore, important for making this expansion into a wider family of devices possible.
The second major part of the related art concerns semiconductor memory circuits. Memory circuits are circuits that can store information usually, but not necessarily, in a digital form. A memory circuit must also provide a means for retrieving the information. The information is stored at a site called the memory cell. There are two primary ways in which semiconductor circuits have been used to store binary data. One is the state of a bistable circuit commonly called the flip-flop, which typically consists of two inverter gates connected in a loop. The other primary method of storing binary information is as the presence or absence of charge on some node in the memory cell. See K. Itoh, "Trends in Megabit DRAM Circuit Design," IEEE I. Solid-State Circuits, vol. 25, pp. 778-89, June 1990, and U.S. Pat. No. 3,387,286, by Dennard. This latter method is commonly used in CMOS dynamic RAMs to achieve small area cells. Functional 64 Mb CMOS dynamic RAMs have been demonstrated recently and it is projected that 1 Gb CMOS memories will be possible by the end of this century. See T. Yamada, Y. Nakata, J. Hasegawa, N. Amano, A. Shibayama, M. Sasago, N. Matsuo, T. Yabu, S. Matsumoto, S. Okada, M. Inoue, "A 64 Mb DRAM with meshed power line and distributed sense amplifier driver," 1991 ISSCC Digest of Technical Papers, pp. 108-9, February 1991, and S. Mori, H. Miyamoto, Y. Morooka, S. Kikuda, M. Suwa, M. Kinoshita, A. Hachisuka, H. Arima, M. Yamada, T. Yoshihara, S. Kayano, "A 45 ns 64 Mb DRAM with a merged match-line test architecture," 1991 ISSCC Digest of Technical Papers, pp. 110-11, February 1991.
CMOS memory cells do not dissipate any power under quiescent conditions, whereas NMOS and bipolar memories dissipate small amounts of power. However, the major disadvantages of the semiconductor memories are the large delay and high power dissipation while accessing and retrieving information. The voltage levels required for storing and retrieving the information are of the order of volts for purely semiconducting memory circuits. The transistors in the memory cells have to be of minimum size so as to increase the memory capacity. However, small transistors have poor interconnection drive capability, and hence the transfer of information from the memory cells to the peripheral detection circuits becomes slow and inefficient. Even with elaborate schemes, the slow transfer of information from the memory cells to the peripheral circuits cannot be avoided in the case of dense memories. See K. Itoh, "Trends in Megabit DRAM Circuit Design," IEEE I. Solid-State Circuits, vol. 25, pp. 778-89, Jun. 1990.
The third major area of related prior art concerns low temperature (having a critical temperature less than 20 kelvins) superconducting memory circuits. In this area of the prior art, binary information is stored as either the presence or absence of a persistent circulating current in a superconducting loop which includes one or more Josephson devices. Alternatively, in some cases, information can be stored as the presence of either a clockwise or counter-clockwise circulating persistent superconducting current in a superconducting loop which includes one or more Josephson devices. The information stored in the cell can be accessed very rapidly and this is their primary advantage. However, operating margins for the superconducting memories are small and it is difficult to scale down the memory cell size without compromising the margins further. See H. Zappe, "Memory-Cell Design in Josephson Technology," IEEE Trans Electron Devices, vol. ED-27, pp. 1870-82, 1980 and Wada, "Josephson Memory Technology," Proc. IEEE, vol. 77, pp. 1194-1207, 1989. The largest fully functional superconducting RAM demonstrated thus far is 1 Kb; this is roughly four orders of magnitude less dense than the CMOS RAMs. See I. Kurosawa, H. Nakagawa, S. Kosaka, M. Aoyagi, S. Takada, "A 1-Kb Josephson Ram Using variable threshold cells," IEEE J. Solid-State Circuits, vol. 24, pp. 1034-39, August 1989.
The most common method of storing information in a superconducting loop is to store zero, one or two flux quanta. To store n flux quanta in a loop, the product of the loop inductance L and the critical current I.sub.c of the Josephson device must be equal to or greater than n .sub..PHI..sbsb.o, where .sub..PHI..sbsb.o is the flux quantum and equals 2.07.times.10.sup.-15 Wb. It is difficult in practice to make I.sub.c large and still retain the current-voltage characteristics of ideal tunnel junctions. This imposes a minimum value on L, which prohibits the memory cell from being chosen to be arbitrarily small, since the loop inductance is proportional to the perimeter of the loop. See H. Zappe, "Memory-Cell Design in Josephson Technology," IEEE Trans Electron Devices, vol. ED-27, pp. 1870-82, 1990; S. Faris, "Basic Design of a Josephson Technology Cache Memory," IBM J. Res. Develop., vol. 24, pp. 143-66, 1980; and C. Mead and L. Conway, Introduction to VLSI System, Reading, Mass.: Addison-Wesley Publishing Company, 1980, Chapter 9. These limitations are well understood by practitioners of the art. Storage of data in terms of such limited number of quanta also results in high bit error rates during detection. For high temperature superconductors (having critical temperatures greater than 20 kelvins) that are operated at high temperatures, for example, 77 kelvins, these considerations pose additional problems. The immature processes and the increase in thermal noise (which is proportional to absolute temperature) necessitate high values of the critical currents for the Josephson devices. Hence, the quiescent power dissipation in the peripheral circuits to address and access the cells is very large.
Memories cells are usually organized in a rectangular (X-Y) array and the state of a particular memory cell is determined by activating a particular word line (conventionally along the X direction) using row decoders and selecting the signal response on the bit lines (conventionally along the Y direction) using column decoders. In conventional CMOS memories, the transistors in the memory cells are of minimum size so as to maximize the cell density. See K. Itoh, "Trends in Megabit DRAM Circuit Design," IEEE I. Solid-State Circuits, vol. 25, pp. 778-89, Jun. 1990 and L. Glasser and D. Dobberpuhl, The Design and Analysis of VLSI Circuits, Reading, Mass.: Addison-Wesley Publishing Company, 1985, Chapter 7. When activated by the word line voltage signal, the state of the cell is transferred to the high capacitance bit lines through a small (high resistance) isolation/pass transistor. This transfer of information from the cell to the bit lines is slow because of the large RC time constants. In the case of dynamic RAMs, the charge on the small cell storage capacitor is shared with the large bit line capacitance and, hence, the bit line signal voltages are very small.
To avoid bit errors due to various noise sources, two bit lines are commonly used per memory cell and the small differential signals between the bit lines are detected by sense amplifiers, typically differential amplifiers. The signal detection by the sense amplifiers introduce additional delays and consume much power. In addition, the sense amplifiers have intrinsic voltage offsets and noise problems which limit their sensitivity. Because of these limitations, prior art CMOS designs sometimes include sophisticated schemes, which introduce additional delays, such as bit-line twisting and partitioning and duplication of sense amplifiers in large dynamic RAMs.
The 64 Mb DRAM built by researchers at Hitachi includes 64,000 sense amplifiers with power dissipation in the sense amplifiers reduced by self-timing the circuits. The read access time of such a memory was estimated to be 60 ns. A 1 Gb DRAM circuit based on such a design will need at least one million such sense amplifiers. See K. Itoh, "Trends in Megabit DRAM Circuit Design," IEEE I. Solid-State Circuits, vol. 25, pp. 778-89, June 1990. Thus, methods which eliminate the need for sensitive sense amplifiers, such as the ones disclosed herein with regard to the present invention, are extremely valuable.
Although there is no charge sharing between the cell and bit lines in static RAMs (SRAMs), the situation is similar to the DRAMs because these SRAM memories are mainly geared for higher speed operation. The RC charging times of the bit lines is unavoidable and it imposes a lower bound on the speed-power product of the memory circuit. To alleviate this problem, sensitive amplifiers using bipolar junction transistors (BiCMOS) have been used in recent designs in order to detect smaller bit line swings. The read access times of 1 Mb SRAMs has been scaled down from 8 ns to 5 ns using an advanced BiCMOS technology. The main drawback is the increased process complexity and power dissipation. Moreover, the sensitivity gains are limited because the RC charging times of the bit lines cannot be avoided. The advantages of BiCMOS technology over a pure CMOS technology is itself questionable when the channel lengths are scaled below 0N5 .sup..mu. m. The problems with both the DRAM and SRAM designs arise mainly due to the voltage-sensing schemes employed to detect small voltage signals on the bit lines.
Therefore, it is an object of this invention to provide novel circuits used in the function of random access memory, wherein the state of memory cells is detected without incurring and being dependent on the semiconductor memory drawbacks such as RC delay in the bit lines, and the need for sense amplifiers, and wherein the state of memory cells is detected without incurring the superconductor memory drawbacks such as the limitations of the size of the inductance loop, and high bit error rates. A further object of the present invention is to provide novel circuits used in the function of random access memory which not only eliminate the semiconductor memory and superconductor memory drawbacks, but also provide fast access times, wide operating margins and low power dissipation, and permit dense packing of the memory cells.